effects. Also see www.ti.com/grace for a GUI- and www.ti.com/msp430ware

; effects. Also see www.ti.com/grace for a GUI- and www.ti.com/msp430ware

; for an API functional library-approach to peripheral configuration.

;

; --/COPYRIGHT--

;******************************************************************************

; MSP430xG46x Demo - Timer_A, Toggle P5.1, TACCR0 Cont. Mode ISR, DCO SMCLK

;

; Description: Toggle P5.1 using software and TA_0 ISR. Toggles every

; 50000 SMCLK cycles. SMCLK provides clock source for TACLK.

; During the TA_0 ISR, P5.1 is toggled and 50000 clock cycles are added

; to TACCR0. TA_0 ISR is triggered every 50000 cycles. CPU is normally off

; and used only during TA_ISR.

; ACLK = 32.768kHz, MCLK = SMCLK = TACLK = default DCO

;

; MSP430xG461x

; -----------------

; /|\| XIN|-

; | | | 32kHz

; --|RST XOUT|-

; | |

; | P5.1|-->LED

;

; S. Karthikeyan/ K.Venkat

; Texas Instruments Inc.

; Dec 2006

; Built with IAR Embedded Workbench Version: 3.41A

;******************************************************************************

#include

;-------------------------------------------------------------------------------

RSEG CSTACK ; Define stack segment

;-------------------------------------------------------------------------------

RSEG CODE ; Assemble to Flash memory

;-----------------------------------------------------------------------------

; ******************* 1. Èíèöèàëèçàöèß òàéìåðà è LCD-äèñïëåß ******************

RESET mov.w #SFE(CSTACK), SP ; Initialize stackpointer

mov.b #LCDON + LCD4MUX + LCDFREQ_128, &LCDACTL ; 4mux LCD, ACLK/128

mov.b #0x0F, &LCDAPCTL0 ; Segments 0-13

mov.b #0x1C, &P5SEL ; set COM pins for LCD

ClearLCD mov.w #20, R15 ; 15 LCD memory bytes to clear

Clear1 mov.b #0, LCDM1(R15) ; Write zeros in LCD RAM locations