to clear display dec R15 ; All LCD mem clear?

; to clear display

dec R15 ; All LCD mem clear?

jc Clear1 ; More LCD mem to clear go, use JC

StopWDT mov.w #WDTPW+WDTHOLD, &WDTCTL ; Stop WDT

SetupFLL bis.b #XCAP14PF, &FLL_CTL0 ; Configure load caps

OFIFGcheck bic.b #OFIFG, &IFG1 ; Clear OFIFG

mov.w #047FFh, R15 ; Wait for OFIFG to set again if

OFIFGwait dec.w R15 ; not stable yet

jnz OFIFGwait

bit.b #OFIFG, &IFG1 ; Has it set again?

jnz OFIFGcheck ; If so, wait some more

SetupP5 bis.b #002h, &P5DIR ; P5.1 output

SetupC0 mov.w #CCIE, &TACCTL0 ; TACCR0 interrupt enabled

; CCIE and CCIFG (bits 4 and 0) are

;more interrupts associated

; with the CCR's.

mov.w #50000, &TACCR0 ;

SetupTA mov.w #TASSEL_2+MC_2, &TACTL ; SMCLK, continuous mode

; ****************** 2. Óñòàíîâêà íà÷àëüíûõ çíà÷åíèé **************************

Mainloop mov.w #01024d, R7 ; number

mov.w #10d, R8 ; skip

mov #18, R13

;bis.w #CPUOFF+GIE, SR ; CPU off, interrupts enabled

;nop ; Required for debugger

;bis.w #GIE, SR ; interrupts enabled

;jmp $

;nop

BEG0:

MOV #00d, R6

MOV.B #0FFh, 90h(R6)

MOV.B #0FFh, 91h(R6)

MOV.B #0FFh, 92h(R6)

MOV.B #0FFh, 93h(R6)

MOV.B #0FFh, 94h(R6)

MOV.B #0FFh, 95h(R6)

; Öèêë èìèòàöèè òàéìåðà

entry: mov #50000, R14

cycle: dec R14

jnz cycle

call #TA0_ISR

jmp entry

; ****************** 3. Îáðàáîò÷èê ïðåðûâàíèß *********************************

TA0_ISR; DEC NUMBER

;------------------------------------------------------------------------------

add.w #50000, &TACCR0 ; Add Offset to TACCR0

dec.w R8

jz run

ret

run:

dec.w R7 ; number

mov.w R7, R4

call #ITOA ; int to string

mov.w #10d, R8