Краткое содержание цикла лекций №1 «Проектирование и производство цифровых сбис нанометрового масштаба»
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- Базовые справочные материалы
- Развернутое содержание цикла лекций № 1 «Проектирование и Производство Цифровых СБИС нанометрового масштаба»
- From Algorithms to Architectures
- Functional Verification
- Modelling Hardware with VHDL
- The Case for Synchronous Design
- Clocking of Synchronous Circuits
- Acquisition of Asynchronous Data
- Gate- and Transistor-Level Design
- Energy Efficiency and Heat Removal
- VLSI Economics and Project Management
- A Primer on CMOS Technology
- Развернутое содержание цикла лекций № 2 «Архитектура высокопроизводительных микропроцессоров и систем на кристалле»
Краткое содержание цикла лекций № 1 «Проектирование и производство цифровых СБИС нанометрового масштаба»
Краткое содержание цикла лекций № 2 «Архитектура высокопроизводительных микропроцессоров и систем на кристалле»
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Развернутое содержание цикла лекций № 1 «Проектирование и Производство Цифровых СБИС нанометрового масштаба»Introduction to Microelectronics1.1 Economic impact 1.2 Concepts and terminology 1.2.1 The Guinness book of records point of view 1.2.2 The marketing point of view 1.2.3 The fabrication point of view 1.2.4 The design engineer’s point of view 1.2.5 The business point of view 1.3 Design flow in digital VLSI 1.3.1 The Y-chart, a map of digital electronic systems 1.3.2 Major stages in VLSI design 1.3.3 Cell libraries 1.3.4 Electronic design automation software 1.4 Field-programmable logic 1.4.1 Configuration technologies 1.4.2 Organization of hardware resources 1.4.3 Commercial products From Algorithms to Architectures2.1 The goals of architecture design 2.2 The architectural antipodes 2.2.1 What makes an algorithm suitable for a dedicated VLSI architecture? 2.2.2 There is plenty of land between the architectural antipodes 2.2.3 Assemblies of general-purpose and dedicated processing units 2.2.4 Coprocessors 2.2.5 Application-specific instruction set processors 2.2.6 Configurable computing 2.2.7 Extendable instruction set processors 2.3 A transform approach to VLSI architecture design 2.3.1 There is room for remodelling in the algorithmic domain . . . 2.3.2 . . . and there is room in the architectural domain 2.3.3 Systems engineers and VLSI designers must collaborate 2.3.4 A graph-based formalism for describing processing algorithms 2.3.5 The isomorphic architecture 2.3.6 Relative merits of architectural alternatives 2.3.7 Computation cycle versus clock period 2.4 Equivalence transforms for combinational computations 2.4.1 Common assumptions 2.4.2 Iterative decomposition 2.4.3 Pipelining 2.4.4 Replication 2.4.5 Time sharing 2.4.6 Associativity transform 2.4.7 Other algebraic transforms 2.5 Options for temporary storage of data 2.5.1 Data access patterns 2.5.2 Available memory configurations and area occupation 2.5.3 Storage capacities 2.5.4 Wiring and the costs of going off-chip 2.5.5 Latency and timing 2.6 Equivalence transforms for nonrecursive computations 2.6.1 Retiming 2.6.2 Pipelining revisited 2.6.3 Systolic conversion 2.6.4 Iterative decomposition and time-sharing revisited 2.6.5 Replication revisited 2.7 Equivalence transforms for recursive computations 2.7.1 The feedback bottleneck 2.7.2 Unfolding of first-order loops 2.7.3 Higher-order loops 2.7.4 Time-variant loops 2.7.5 Nonlinear or general loops 2.7.6 Pipeline interleaving is not an equivalence transform 2.8 Generalizations of the transform approach 2.8.1 Generalization to other levels of detail 2.8.2 Bit-serial architectures 2.8.3 Distributed arithmetic 2.8.4 Generalization to other algebraic structures 2.9.2 The grand architectural alternatives from an energy point of view 2.9.3 A guide to evaluating architectural alternatives
3.1.1 Formal specification 3.1.2 Rapid prototyping 3.2 Developing an adequate simulation strategy 3.2.1 What does it take to uncover a design flaw during simulation? 3.2.2 Stimulation and response checking must occur automatically 3.2.3 Exhaustive verification remains an elusive goal 3.2.4 All partial verification techniques have their pitfalls 3.2.5 Collecting test cases from multiple sources helps 3.2.6 Assertion-based verification helps 3.2.7 Separating test development from circuit design helps 3.2.8 Virtual prototypes help to generate expected responses 3.3 Reusing the same functional gauge throughout the entire design cycle 3.3.1 Alternative ways to handle stimuli and expected responses 3.3.2 Modular testbench design 3.3.3 A well-defined schedule for stimuli and responses 3.3.4 Trimming run times by skipping redundant simulation sequences 3.3.5 Abstracting to higher-level transactions on higher-level data 3.3.6 Absorbing latency variations across multiple circuit models
4.1.1 Why hardware synthesis? 4.1.2 What are the alternatives to VHDL? 4.1.3 What are the origins and aspirations of the IEEE 1076 standard? 4.1.4 Why bother learning hardware description languages? 4.1.5 Agenda 4.2 Key concepts and constructs of VHDL 4.2.1 Circuit hierarchy and connectivity 4.2.2 Concurrent processes and process interaction 4.2.3 A discrete replacement for electrical signals 4.2.4 An event-based concept of time for governing simulation 4.2.5 Facilities for model parametrization 4.2.6 Concepts borrowed from programming languages 4.3 Putting VHDL to service for hardware synthesis 4.3.1 Synthesis overview 4.3.2 Data types 4.3.3 Registers, finite state machines, and other sequential subcircuits 4.3.4 RAMs, ROMs, and other macrocells 4.3.5 Circuits that must be controlled at the netlist level 4.3.6 Timing constraints 4.3.7 Limitations and caveats for synthesis 4.3.8 How to establish a register transfer-level model step by step 4.4 Putting VHDL to service for hardware simulation 4.4.1 Ingredients of digital simulation 4.4.2 Anatomy of a generic testbench 4.4.3 Adapting to a design problem at hand 4.4.4 The VITAL modelling standard IEEE 1076.4 4.8.1 Protected shared variables IEEE 1076a 4.8.2 The analog and mixed-signal extension IEEE 1076.1 4.8.3 Mathematical packages for real and complex numbers IEEE 1076.2 4.8.4 The arithmetic packages IEEE 1076.3 4.8.5 A language subset earmarked for synthesis IEEE 1076.6 4.8.6 The standard delay format (SDF) IEEE 1497 4.8.7 A handy compilation of type conversion functions 4.9 Appendix III: Examples of VHDL models 4.9.1 Combinational circuit models 4.9.2 Mealy, Moore, and Medvedev machines 4.9.3 State reduction and state encoding 4.9.4 Simulation testbenches 4.9.5 Working with VHDL tools from different vendors The Case for Synchronous Design5.1 Introduction 5.2 The grand alternatives for regulating state changes 5.2.1 Synchronous clocking 5.2.2 Asynchronous clocking 5.2.3 Self-timed clocking 5.3 Why a rigorous approach to clocking is essential in VLSI 5.3.1 The perils of hazards 5.3.2 The pros and cons of synchronous clocking 5.3.3 Clock-as-clock-can is not an option in VLSI 5.3.4 Fully self-timed clocking is not normally an option either 5.3.5 Hybrid approaches to system clocking 5.4 The dos and don’ts of synchronous circuit design 5.4.1 First guiding principle: Dissociate signal classes! 5.4.2 Second guiding principle: Allow circuits to settle before clocking! 5.4.3 Synchronous design rules at a more detailed level 5.7 On identifying signals 5.7.1 Signal class 5.7.2 Active level 5.7.3 Signaling waveforms 5.7.4 Three-state capability 5.7.5 Inputs, outputs, and bidirectional terminals 5.7.6 Present state vs. next state 5.7.7 Syntactical conventions 5.7.8 A note on upper- and lower-case letters in VHDL 5.7.9 A note on the portability of names across EDA platforms
6.1.1 Agenda 6.1.2 Timing quantities related to clock distribution 6.2 How much skew and jitter does a circuit tolerate? 6.2.1 Basics 6.2.2 Single-edge-triggered one-phase clocking 6.2.3 Dual-edge-triggered one-phase clocking 6.2.4 Symmetric level-sensitive two-phase clocking 6.2.5 Unsymmetric level-sensitive two-phase clocking 6.2.6 Single-wire level-sensitive two-phase clocking 6.2.7 Level-sensitive one-phase clocking and wave pipelining 6.3 How to keep clock skew within tight bounds 6.3.1 Clock waveforms 6.3.2 Collective clock buffers 6.3.3 Distributed clock buffer trees 6.3.4 Hybrid clock distribution networks 6.3.5 Clock skew analysis 6.4 How to achieve friendly input/output timing 6.4.1 Friendly as opposed to unfriendly I/O timing 6.4.2 Impact of clock distribution delay on I/O timing 6.4.3 Impact of PTV variations on I/O timing 6.4.4 Registered inputs and outputs 6.4.5 Adding artificial contamination delay to data inputs 6.4.6 Driving input registers from an early clock 6.4.7 Tapping a domain’s clock from the slowest component therein 6.4.8 “Zero-delay” clock distribution by way of a DLL or PLL 6.5 How to implement clock gating properly 6.5.1 Traditional feedback-type registers with enable 6.5.2 A crude and unsafe approach to clock gating 6.5.3 A simple clock gating scheme that may work under certain conditions 6.5.4 Safe clock gating schemes
7.2 The data consistency problem of vectored acquisition 7.2.1 Plain bit-parallel synchronization 7.2.2 Unit-distance coding 7.2.3 Suppression of crossover patterns 7.2.4 Handshaking 7.2.5 Partial handshaking 7.3 The data consistency problem of scalar acquisition 7.3.1 No synchronization whatsoever 7.3.2 Synchronization at multiple places 7.3.3 Synchronization at a single place 7.3.4 Synchronization from a slow clock 7.4 Metastable synchronizer behavior 7.4.1 Marginal triggering and how it becomes manifest 7.4.2 Repercussions on circuit functioning 7.4.3 A statistical model for estimating synchronizer reliability 7.4.4 Plesiochronous interfaces 7.4.5 Containment of metastable behavior Gate- and Transistor-Level Design8.1 CMOS logic gates 8.1.1 The MOSFET as a switch 8.1.2 The inverter 8.1.3 Simple CMOS gates 8.1.4 Composite or complex gates 8.1.5 Gates with high-impedance capabilities 8.1.6 Parity gates 8.1.7 Adder slices 8.2 CMOS bistables 8.2.1 Latches 8.2.2 Function latches 8.2.3 Single-edge-triggered flip-flops 8.2.4 The mother of all flip-flops 8.2.5 Dual-edge-triggered flip-flops 8.3 CMOS on-chip memories 8.3.1 Static RAM 8.3.2 Dynamic RAM 8.3.3 Other differences and commonalities 8.4 Electrical CMOS contraptions 8.4.1 Snapper 8.4.2 Schmitt trigger 8.4.3 Tie-off cells 8.4.4 Filler cell or fillcap 8.4.5 Level shifters and input/output buffers 8.4.6 Digitally adjustable delay lines 8.5 Pitfalls 8.5.1 Busses and three-state nodes 8.5.2 Transmission gates and other bidirectional components 8.5.3 What do we mean by safe design? 8.5.4 Microprocessor interface circuits 8.5.5 Mechanical contacts 8.7 Summary on electrical MOSFET models 8.7.1 Naming and counting conventions 8.7.2 The Sah model 8.7.3 The Shichman–Hodges model 8.7.4 The alpha-power-law model 8.7.5 Second-order effects 8.7.6 Effects not normally captured by transistor models Energy Efficiency and Heat Removal9.1 What does energy get dissipated for in CMOS circuits? 9.1.1 Charging and discharging of capacitive loads 9.1.2 Crossover currents 9.1.3 Resistive loads 9.1.4 Leakage currents 9.1.5 Total energy dissipation 9.1.6 CMOS voltage scaling 9.2 How to improve energy efficiency 9.2.1 General guidelines 9.2.2 How to reduce dynamic dissipation 9.2.3 How to counteract leakage 9.3 Heat flow and heat removal 9.4 Contributions to node capacitance 9.5 Unorthodox approaches 9.5.1 Subthreshold logic 9.5.2 Voltage-swing-reduction techniques 9.5.3 Adiabatic logic
Signal Integrity10.1 Introduction 10.1.1 How does noise enter electronic circuits? 10.1.2 How does noise affect digital circuits? 10.1.3 Agenda 10.2 Crosstalk 10.3 Ground bounce and supply droop 10.3.1 Coupling mechanisms due to common series impedances 10.3.2 Where do large switching currents originate? 10.3.3 How severe is the impact of ground bounce? 10.4 How to mitigate ground bounce 10.4.1 Reduce effective series impedances 10.4.2 Separate polluters from potential victims 10.4.3 Avoid excessive switching currents 10.4.4 Safeguard noise margins 10.5 Conclusions 10.6 Derivation of second-order approximation Physical Design11.1 Agenda 11.2 Conducting layers and their characteristics 11.2.1 Geometric properties and layout rules 11.2.2 Electrical properties 11.2.3 Connecting between layers 11.2.4 Typical roles of conducting layers 11.3 Cell-based back-end design 11.3.1 Floorplanning 11.3.2 Identify major building blocks and clock domains 11.3.3 Establish a pin budget 11.3.4 Find a relative arrangement of all major building blocks 11.3.5 Plan power, clock, and signal distribution 11.3.6 Place and route (P&R) 11.3.7 Chip assembly 11.4 Packaging 11.4.1 Wafer sorting 11.4.2 Wafer testing 11.4.3 Backgrinding and singulation 11.4.4 Encapsulation 11.4.5 Final testing and binning 11.4.6 Bonding diagram and bonding rules 11.4.7 Advanced packaging techniques 11.4.8 Selecting a packaging technique 11.5 Layout at the detail level 11.5.1 Objectives of manual layout design 11.5.2 Layout design is no WYSIWYG business 11.5.3 Standard cell layout 11.5.4 Sea-of-gates macro layout 11.5.5 SRAM cell layout 11.5.6 Lithography-friendly layouts help improve fabrication yield 11.5.7 The mesh, a highly efficient and popular layout arrangement 11.6 Preventing electrical overstress 11.6.1 Electromigration 11.6.2 Electrostatic discharge 11.6.3 Latch-up 11.8 Geometric quantities advertized in VLSI 11.9 On coding diffusion areas in layout drawings 11.10 Sheet resistance Design Verification12.1 Uncovering timing problems 12.1.1 What does simulation tell us about timing problems? 12.1.2 How does timing verification help? 12.2 How accurate are timing data? 12.2.1 Cell delays 12.2.2 Interconnect delays and layout parasitics 12.2.3 Making realistic assumptions is the point 12.3 More static verification techniques 12.3.1 Electrical rule check 12.3.2 Code inspection 12.4 Post-layout design verification 12.4.1 Design rule check 12.4.2 Manufacturability analysis 12.4.3 Layout extraction 12.4.4 Layout versus schematic 12.4.5 Equivalence checking 12.4.6 Post-layout timing verification 12.4.7 Power grid analysis 12.4.8 Signal integrity analysis 12.4.9 Post-layout simulations 12.4.10 The overall picture 12.7 Cell and library characterization 12.8 Equivalent circuits for interconnect modelling
13.2 Models of industrial cooperation 13.2.1 Systems assembled from standard parts exclusively 13.2.2 Systems built around program-controlled processors 13.2.3 Systems designed on the basis of field-programmable logic 13.2.4 Systems designed on the basis of semi-custom ASICs 13.2.5 Systems designed on the basis of full-custom ASICs 13.3 Interfacing within the ASIC industry 13.3.1 Handoff points for IC design data 13.3.2 Scopes of IC manufacturing services 13.4 Virtual components 13.4.1 Copyright protection vs. customer information 13.4.2 Design reuse demands better quality and more thorough verification 13.4.3 Many existing virtual components need to be reworked 13.4.4 Virtual components require follow-up services 13.4.5 Indemnification provisions 13.4.6 Deliverables of a comprehensive VC package 13.4.7 Business models 13.5 The costs of integrated circuits 13.5.1 The impact of circuit size 13.5.2 The impact of the fabrication process 13.5.3 The impact of volume 13.5.4 The impact of configurability 13.5.5 Digest 13.6 Fabrication avenues for small quantities 13.6.1 Multi-project wafers 13.6.2 Multi-layer reticles 13.6.3 Electron beam lithography 13.6.4 Laser programming 13.6.5 Hardwired FPGAs and structured ASICs 13.6.6 Cost trading 13.7 The market side 13.7.1 Ingredients of commercial success 13.7.2 Commercialization stages and market priorities 13.7.3 Service versus product 13.7.4 Product grading 13.8 Making a choice 13.8.1 ASICs yes or no? 13.8.2 Which implementation technique should one adopt? 13.8.3 What if nothing is known for sure? 13.8.4 Can system houses afford to ignore microelectronics? 13.9 Keys to successful VLSI design 13.9.1 Project definition and marketing 13.9.2 Technical management 13.9.3 Engineering 13.9.4 Verification 13.9.5 Myths 13.10 Appendix: Doing business in microelectronics 13.10.1 Checklists for evaluating business partners and design kits 13.10.2 Virtual component providers 13.10.3 Selected low-volume providers 13.10.4 Cost estimation helps A Primer on CMOS Technology14.1 The essence of MOS device physics 14.1.1 Energy bands and electrical conduction 14.1.2 Doping of semiconductor materials 14.1.3 Junctions, contacts, and diodes 14.1.4 MOSFETs 14.2 Basic CMOS fabrication flow 14.2.1 Key characteristics of CMOS technology 14.2.2 Front-end-of-line fabrication steps 14.2.3 Back-end-of-line fabrication steps 14.2.4 Process monitoring 14.2.5 Photolithography 14.3 Variations on the theme 14.3.1 Copper has replaced aluminum as interconnect material 14.3.2 Low-permittivity interlevel dielectrics are replacing silicon dioxide 14.3.3 High-permittivity gate dielectrics to replace silicon dioxide 14.3.4 Strained silicon and SiGe technology 14.3.5 Metal gates bound to come back 14.3.6 Silicon-on-insulator (SOI) technology Outlook15.1 Evolution paths for CMOS technology 15.1.1 Classic device scaling 15.1.2 The search for new device topologies 15.1.3 Vertical integration 15.1.4 The search for better semiconductor materials 15.2 Is there life after CMOS? 15.2.1 Non-CMOS data storage 15.2.2 Non-CMOS data processing 15.3 Technology push 15.3.1 The so-called industry “laws” and the forces behind them 15.3.2 Industrial roadmaps 15.4 Market pull 15.5 Evolution paths for design methodology 15.5.1 The productivity problem 15.5.2 Fresh approaches to architecture design 15.6 Six grand challenges 15.7 Non-semiconductor storage technologies for comparison Развернутое содержание цикла лекций № 2 «Архитектура высокопроизводительных микропроцессоров и систем на кристалле»
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