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is never used or assigned. This unconnected signal will be trimmed during the optimization process.

Register equivalent to has been removed

Register equivalent to has been removed

Found 16x8-bit ROM for signal .

Found 1-bit register for signal .

Found 31-bit register for signal .

Found 31-bit adder for signal created at line 54.

Found 8-bit register for signal .

Found 1-bit 8-to-1 multiplexer for signal created at line 60.

Summary:

inferred 1 ROM(s).

inferred 40 D-type flip-flop(s).

inferred 1 Adder/Subtractor(s).

inferred 1 Multiplexer(s).

Unit synthesized.

=========================================================================

HDL Synthesis Report


Macro Statistics

# ROMs : 1

16x8-bit ROM : 1

# Adders/Subtractors : 1

31-bit adder : 1

# Registers : 3

1-bit register : 1

31-bit register : 1

8-bit register : 1

# Multiplexers : 1

1-bit 8-to-1 multiplexer : 1
=========================================================================
=========================================================================

* Advanced HDL Synthesis *

=========================================================================

=========================================================================

Advanced HDL Synthesis Report
Macro Statistics

# ROMs : 1

16x8-bit ROM : 1

# Adders/Subtractors : 1

31-bit adder : 1

# Registers : 40

Flip-Flops : 40

# Multiplexers : 1

1-bit 8-to-1 multiplexer : 1
=========================================================================
=========================================================================

* Low Level Synthesis *

=========================================================================

WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.


Optimizing unit ...

INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed :

INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed :

INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed :

INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed :
Mapping all equations...

Building and optimizing final netlist ...

Found area constraint ratio of 100 (+ 5) on block converter, actual ratio is 0.
Final Macro Processing ...
=========================================================================

Final Register Report


Macro Statistics

# Registers : 38

Flip-Flops : 38
=========================================================================
=========================================================================

* Partition Report *

=========================================================================
Partition Implementation Status

-------------------------------


No Partitions were found in this design.
-------------------------------
=========================================================================

* Final Report *

=========================================================================

Final Results

RTL Top Level Output File Name : converter.ngr

Top Level Output File Name : converter

Output Format : NGC

Optimization Goal : Speed

Keep Hierarchy : No
Design Statistics

# IOs : 31


Cell Usage :

# BELS : 136

# GND : 1

# INV : 1

# LUT1 : 30

# LUT2 : 4

# LUT3 : 2

# LUT4 : 18

# MUXCY : 38

# MUXF5 : 9

# MUXF6 : 1

# VCC : 1

# XORCY : 31

# FlipFlops/Latches : 38

# FDE : 38

# Clock Buffers : 1

# BUFGP : 1

# IO Buffers : 20

# IBUF : 17

# OBUF : 3

=========================================================================
Device utilization summary:

---------------------------


Selected Device : 3s500efg320-5
Number of Slices: 49 out of 4656 1%

Number of Slice Flip Flops: 38 out of 9312 0%

Number of 4 input LUTs: 55 out of 9312 0%

Number of IOs: 31

Number of bonded IOBs: 21 out of 232 9%

Number of GCLKs: 1 out of 24 4%


---------------------------

Partition Resource Summary:

---------------------------
No Partitions were found in this design.
---------------------------

=========================================================================

TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT

GENERATED AFTER PLACE-and-ROUTE.
Clock Information:

------------------

-----------------------------------+------------------------+-------+

Clock Signal | Clock buffer(FF name) | Load |

-----------------------------------+------------------------+-------+

clk | BUFGP | 38 |

-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:

----------------------------------------

No asynchronous control signals found in this design
Timing Summary:

---------------

Speed Grade: -5
Minimum period: 9.034ns (Maximum Frequency: 110.694MHz)

Minimum input arrival time before clock: 4.905ns

Maximum output required time after clock: 4.134ns

Maximum combinational path delay: No path found


Timing Detail:

--------------

All values displayed in nanoseconds (ns)
=========================================================================

Timing constraint: Default period analysis for Clock 'clk'

Clock period: 9.034ns (frequency: 110.694MHz)

Total number of paths / destination ports: 4976 / 32

-------------------------------------------------------------------------

Delay: 9.034ns (Levels of Logic = 34)

Source: vard_1 (FF)

Destination: blue (FF)

Source Clock: clk rising

Destination Clock: clk rising


Data Path: vard_1 to blue

Gate Net


Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

FDE:C->Q 1 0.514 0.509 vard_1 (vard_1)

LUT1:I0->O 1 0.612 0.000 Madd_vard_addsub0000_cy<1>_rt (Madd_vard_addsub0000_cy<1>_rt)

MUXCY:S->O 1 0.404 0.000 Madd_vard_addsub0000_cy<1> (Madd_vard_addsub0000_cy<1>)

MUXCY:CI->O 1 0.051 0.000 Madd_vard_addsub0000_cy<2> (Madd_vard_addsub0000_cy<2>)

MUXCY:CI->O 1 0.051 0.000 Madd_vard_addsub0000_cy<3> (Madd_vard_addsub0000_cy<3>)

MUXCY:CI->O 1 0.051 0.000 Madd_vard_addsub0000_cy<4> (Madd_vard_addsub0000_cy<4>)

MUXCY:CI->O 1 0.051 0.000 Madd_vard_addsub0000_cy<5> (Madd_vard_addsub0000_cy<5>)

MUXCY:CI->O 1 0.051 0.000 Madd_vard_addsub0000_cy<6> (Madd_vard_addsub0000_cy<6>)

MUXCY:CI->O 1 0.051 0.000 Madd_vard_addsub0000_cy<7> (Madd_vard_addsub0000_cy<7>)

MUXCY:CI->O 1 0.051 0.000 Madd_vard_addsub0000_cy<8> (Madd_vard_addsub0000_cy<8>)

MUXCY:CI->O 1 0.051 0.000 Madd_vard_addsub0000_cy<9> (Madd_vard_addsub0000_cy<9>)

MUXCY:CI->O 1 0.051 0.000 Madd_vard_addsub0000_cy<10> (Madd_vard_addsub0000_cy<10>)

MUXCY:CI->O 1 0.051 0.000 Madd_vard_addsub0000_cy<11> (Madd_vard_addsub0000_cy<11>)

MUXCY:CI->O 1 0.051 0.000 Madd_vard_addsub0000_cy<12> (Madd_vard_addsub0000_cy<12>)

MUXCY:CI->O 1 0.051 0.000 Madd_vard_addsub0000_cy<13> (Madd_vard_addsub0000_cy<13>)

MUXCY:CI->O 1 0.051 0.000 Madd_vard_addsub0000_cy<14> (Madd_vard_addsub0000_cy<14>)

MUXCY:CI->O 1 0.051 0.000 Madd_vard_addsub0000_cy<15> (Madd_vard_addsub0000_cy<15>)

MUXCY:CI->O 1 0.051 0.000 Madd_vard_addsub0000_cy<16> (Madd_vard_addsub0000_cy<16>)

MUXCY:CI->O 1 0.051 0.000 Madd_vard_addsub0000_cy<17> (Madd_vard_addsub0000_cy<17>)

MUXCY:CI->O 1 0.051 0.000 Madd_vard_addsub0000_cy<18> (Madd_vard_addsub0000_cy<18>)

MUXCY:CI->O 1 0.051 0.000 Madd_vard_addsub0000_cy<19> (Madd_vard_addsub0000_cy<19>)

MUXCY:CI->O 1 0.051 0.000 Madd_vard_addsub0000_cy<20> (Madd_vard_addsub0000_cy<20>)

XORCY:CI->O 2 0.699 0.532 Madd_vard_addsub0000_xor<21> (vard_addsub0000<21>)

LUT3:I0->O 1 0.612 0.000 vard_cmp_eq0001_wg_lut<0> (vard_cmp_eq0001_wg_lut<0>)

MUXCY:S->O 1 0.404 0.000 vard_cmp_eq0001_wg_cy<0> (vard_cmp_eq0001_wg_cy<0>)

MUXCY:CI->O 1 0.052 0.000 vard_cmp_eq0001_wg_cy<1> (vard_cmp_eq0001_wg_cy<1>)

MUXCY:CI->O 1 0.052 0.000 vard_cmp_eq0001_wg_cy<2> (vard_cmp_eq0001_wg_cy<2>)

MUXCY:CI->O 1 0.052 0.000 vard_cmp_eq0001_wg_cy<3> (vard_cmp_eq0001_wg_cy<3>)

MUXCY:CI->O 1 0.052 0.000 vard_cmp_eq0001_wg_cy<4> (vard_cmp_eq0001_wg_cy<4>)

MUXCY:CI->O 1 0.052 0.000 vard_cmp_eq0001_wg_cy<5> (vard_cmp_eq0001_wg_cy<5>)

MUXCY:CI->O 1 0.052 0.000 vard_cmp_eq0001_wg_cy<6> (vard_cmp_eq0001_wg_cy<6>)

MUXCY:CI->O 6 0.399 0.638 vard_cmp_eq0001_wg_cy<7> (vard_cmp_eq0001)

LUT2:I1->O 3 0.612 0.451 vard_mux0000<1>1 (vard_mux0000<1>)

MUXF5:S->O 1 0.641 0.000 Mmux_vgad_mux0000_4_f5 (Mmux_vgad_mux0000_4_f5)

MUXF6:I0->O 1 0.451 0.000 Mmux_vgad_mux0000_2_f6 (vgad_mux0000)

FDE:D 0.268 blue

----------------------------------------

Total 9.034ns (6.904ns logic, 2.130ns route)

(76.4% logic, 23.6% route)
=========================================================================

Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'

Total number of paths / destination ports: 358 / 44

-------------------------------------------------------------------------

Offset: 4.905ns (Levels of Logic = 3)

Source: code<3> (PAD)

Destination: vgad_1 (FF)

Destination Clock: clk rising


Data Path: code<3> to vgad_1

Gate Net


Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

IBUF:I->O 1 1.106 0.509 code_3_IBUF (code_3_IBUF)

LUT4:I0->O 1 0.612 0.509 blue_cmp_eq000010 (blue_cmp_eq000010)

LUT2:I0->O 38 0.612 1.074 blue_cmp_eq000023 (blue_cmp_eq0000)

FDE:CE 0.483 vgad_1

----------------------------------------

Total 4.905ns (2.813ns logic, 2.092ns route)

(57.3% logic, 42.7% route)
=========================================================================

Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'

Total number of paths / destination ports: 3 / 3

-------------------------------------------------------------------------

Offset: 4.134ns (Levels of Logic = 1)

Source: blue (FF)

Destination: blue (PAD)

Source Clock: clk rising


Data Path: blue to blue

Gate Net


Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

FDE:C->Q 3 0.514 0.451 blue (red_OBUF)

OBUF:I->O 3.169 blue_OBUF (blue)

----------------------------------------

Total 4.134ns (3.683ns logic, 0.451ns route)

(89.1% logic, 10.9% route)
=========================================================================

Total REAL time to Xst completion: 10.00 secs

Total CPU time to Xst completion: 9.39 secs

-->
Total memory usage is 186828 kilobytes


Number of errors : 0 ( 0 filtered)

Number of warnings : 6 ( 0 filtered)

Number of infos : 4 ( 0 filtered)


Извеждане на сигнала през VGA порта (синхронизиращ генератор)
Тази част от програмата цели да изгради синхронизиращ генератор, чрез който да се предадат данните от системата към монитора. За целта е необходимо изграждането на тактов генератор на 25MHz, вертикален и хоризонтален синхронизиращ сигнал, както и на брояч на редовете и колоните по които ще става изписването.

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity vga is

port(clk, reset : in std_logic;

red, green, blue : in std_logic;

r, g, b, hsync, vsync : out std_logic;

row : out std_logic_vector(8 downto 0);

column : out std_logic_vector(9 downto 0)

);

end vga;



architecture synt of vga is

signal clk25 : std_logic;

signal videoon, videov, videoh : std_logic;

signal hcount, vcount : std_logic_vector(9 downto 0);


begin

-- generate a 25Mhz clock

process (clk)

begin


if clk'event and clk='1' then

if (clk25 = '0') then

clk25 <= '1';

else


clk25 <= '0';

end if;


end if;

end process;

hcounter: process (clk25, reset) --define horizontal counter

begin


if reset='1' then

hcount <= (others => '0');

else

if (clk25'event and clk25='1') then



if hcount=799

then hcount <= (others => '0');

else hcount <= hcount + 1;

end if;


end if;

end if;


end process;

process (hcount) -- define column number creation

begin

videoh <= '1';



column <= hcount;

if hcount>639

then videoh <= '0';

column <= (others => '0');

end if;

end process;



vcounter: process (clk25, reset) --define vertical counter

begin


if reset='1'

then vcount <= (others => '0');

else

if (clk25'event and clk25='1')



then

if hcount=699

then

if vcount=524



then

vcount <= (others => '0');

else vcount <= vcount + 1;

end if;


end if;

end if;


end if;

end process;

process (vcount) -- defineing row number

begin


videov <= '1';

row <= vcount(8 downto 0);

if vcount>479

then


videov <= '0';

row <= (others => '0');

end if;

end process;



sync: process (clk25, reset) -- syncronization process

begin


if reset='1'

then hsync <= '0';

vsync <= '0';

else


if (clk25'event and clk25='1')

then


if (hcount<=755 and hcount>=659)

then hsync <= '0';

else hsync <= '1';

end if;


if (vcount<=494 and vcount>=493)

then vsync <= '0';

else vsync <= '1';

end if;


end if;

end if;


end process;

videoon <= videoh and videov;


colors: process (clk25, reset) --setting output signals

begin


if (reset='1')

then


r <= '0';

g <= '0';

b <= '0';

elsif (clk25'event and clk25='1')

then

r <= red;



g <= green;

b <= blue;

end if;

end process;



end synt;
На фигурата по-долу е показан симулационния модел на тази част от програмата. Тъй като времето за един пълен цикъл на опресняване е почти 8ms, фигурата е с по-едър мащаб, като целта е да се видят основно сигналите за хоризонтална и вертикална синхронизация.

Резултатът от синтеза е:


Release 12.3 - xst M.70d (nt64)

Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.

--> Parameter TMPDIR set to xst/projnav.tmp

Total REAL time to Xst completion: 0.00 secs

Total CPU time to Xst completion: 0.07 secs

--> Parameter xsthdpdir set to xst

Total REAL time to Xst completion: 0.00 secs

Total CPU time to Xst completion: 0.07 secs

--> Reading design: vga.prj
TABLE OF CONTENTS

1) Synthesis Options Summary

2) HDL Compilation

3) Design Hierarchy Analysis

4) HDL Analysis

5) HDL Synthesis

5.1) HDL Synthesis Report

6) Advanced HDL Synthesis

6.1) Advanced HDL Synthesis Report

7) Low Level Synthesis

8) Partition Report

9) Final Report

9.1) Device utilization summary

9.2) Partition Resource Summary

9.3) TIMING REPORT

=========================================================================

* Synthesis Options Summary *

=========================================================================

---- Source Parameters

Input File Name : "vga.prj"

Input Format : mixed

Ignore Synthesis Constraint File : NO


---- Target Parameters

Output File Name : "vga"

Output Format : NGC

Target Device : xc3s500e-5-fg320


---- Source Options

Top Module Name : vga

Automatic FSM Extraction : YES

FSM Encoding Algorithm : Auto

Safe Implementation : No

FSM Style : LUT

RAM Extraction : Yes

RAM Style : Auto

ROM Extraction : Yes

Mux Style : Auto

Decoder Extraction : YES

Priority Encoder Extraction : Yes

Shift Register Extraction : YES

Logical Shifter Extraction : YES

XOR Collapsing : YES

ROM Style : Auto

Mux Extraction : Yes

Resource Sharing : YES

Asynchronous To Synchronous : NO

Multiplier Style : Auto

Automatic Register Balancing : No
---- Target Options

Add IO Buffers : YES

Global Maximum Fanout : 500

Add Generic Clock Buffer(BUFG) : 24

Register Duplication : YES

Slice Packing : YES

Optimize Instantiated Primitives : NO

Use Clock Enable : Yes

Use Synchronous Set : Yes

Use Synchronous Reset : Yes

Pack IO Registers into IOBs : Auto

Equivalent register Removal : YES


---- General Options

Optimization Goal : Speed

Optimization Effort : 1

Keep Hierarchy : No

Netlist Hierarchy : As_Optimized

RTL Output : Yes

Global Optimization : AllClockNets

Read Cores : YES

Write Timing Constraints : NO

Cross Clock Analysis : NO

Hierarchy Separator : /

Bus Delimiter : <>

Case Specifier : Maintain

Slice Utilization Ratio : 100

BRAM Utilization Ratio : 100

Verilog 2001 : YES

Auto BRAM Packing : NO

Slice Utilization Ratio Delta : 5


=========================================================================

=========================================================================

* HDL Compilation *

=========================================================================

Compiling vhdl file "D:/Desktop/Dian/TU/tu work/MPIS/signs_on_display/VGA/vga/vga.vhd" in Library work.

Entity compiled.

Entity (Architecture ) compiled.
=========================================================================

* Design Hierarchy Analysis *

=========================================================================

Analyzing hierarchy for entity in library (architecture ).

=========================================================================

* HDL Analysis *

=========================================================================

Analyzing Entity in library (Architecture ).

Entity analyzed. Unit generated.

=========================================================================

* HDL Synthesis *

=========================================================================


Performing bidirectional port resolution...
Synthesizing Unit .

Related source file is "D:/Desktop/Dian/TU/tu work/MPIS/signs_on_display/VGA/vga/vga.vhd".

WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Found 1-bit register for signal .

Found 1-bit register for signal .

Found 1-bit register for signal .

Found 1-bit register for signal


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Достарыңызбен бөлісу:




Технически Университет - София

МПИС

Курсов Проект

Тема: Надписи върху дисплей


Разработили:

Диан Милчев Илиев Фак.№ 101207035 - ФЕТТ - гр. 43

Тодор Петров Суванджиев Фак.№ 101207018 - ФЕТТ - гр. 43

Симеон Иванов Джанджев Фак.№ 101207113 - ФЕТТ - гр. 43

Дата: 25.03.2011г.

Гр. София

Ръководител:.....................................

(гл.ас Василий Чумаченко)

Съдържание



Страница

1

Увод

3

2

Техническо задание

4

3

Блокова схема

5

4

VHDL код

6































































Увод
В практиката често се налага извеждането на различна по характер информация върху дисплей - за информационни табла, съобщения и т.н. Голяма част от съвременните устройства за визуализиране са снабдени с т.нар VGA портове. VGA (абревиатура от английски: Video Graphics Array — видео графичен масив) е видео стандарт с аналогов изходен видеосигнал. Той се използва най-често за извеждане на сигналите от графичните карти на персоналните компютри към съответните средства за визуализация - различни монитори, мултимедийни проектори и др.

Поради голямото разнообразие на визуализиращи средства съвместими с този вид порт, разработването на системата за визуализиране на надписи ще се съсредоточи върху управлението на потока от данни именно върху този тип портове.

Избора на начин за въвеждането на информация (надписи) също има аналогични съображения - подходящо е използването на широко разпростаранените компютърни клавиатури с PS/2 конектори.

Самата система за преобразуване на данните от бутоните на клавиатурата в надписи върху дисплей е съсредоточена върху развойната среда Digilent Nexys2 Board с Xilinx Spartan-3 FPGA чип.




Технически Университет - София

ЕУСКУ


Техническо задание

Тема: Надписи вуърху дисплей

Изходни данни:





  1. Надписите да се извеждат на дисплей посредством VGA порт



  2. Въвеждането на надписа да става посредством стандартна клавиатура и през PS/2 порт




  1. Да се използва развойна среда Digilent Nexys2 Board с Xilinx Spartan-3 FPGA

Блокова схема


Следващата блокова схема показва алгоритъма на работа на системата.

Блоковата схема дадена по-долу илюстрира структурата на система:

VHDL код


  1. Приемане на информацията от PS/2 порта (Входен декодиращ блок)

Текущия фрагмент от програмата е за обработване на входния поток от данни от клавиатурата. За да може да се провери изпълнимостта на кода преди да се разработи цялата програма е направена малка модификация състояща се в това че след приемането на входната информация от клавиятурата, тя се декодира в код за 7 сегментен индикатор и се визуализира посредством индикатора на развойната среда.


library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all; -- Дефинират се използваните библиотеки
entity ccc is -- Дефинират се използваните входно-изходни портове

port(clk,ps2clk,data:in std_logic;

led:out std_logic_vector(7 downto 0));

end ccc;


architecture frame of ccc is

signal temp:std_logic_vector(3 downto 0);

signal byte:std_logic_vector(8 downto 0);

signal ready:std_logic;

signal code:std_logic_vector(7 downto 0);
begin

process(ps2clk,data)

begin

if(ps2clk'event and ps2clk='0') then



if(data='0' and ready='0')then

ready<='1';

temp<="0000";

elsif (ready='1') then

if temp<"1001" then

temp<=temp+1;

byte(7 downto 0)<=byte(8 downto 1); -- зареждане на информацията във входен буфер

byte(8)<=data;

else

ready<='0';



code<=byte(7 downto 0); --прехвърляме на информацията от входния буфер в работна променлива

temp<="0000";

end if;

end if;


end if;

case code is -- Преобразуват се входните данни в необходимия формат (за 7 сегментен индикатор)

when "01000101"=>led<="11000000"; --0

when "00010110"=>led<="11111001"; --1

when "00011110"=>led<="10100100"; --2

when "00100110"=>led<="10110000"; --3

when "00100101"=>led<="10011001"; --4

when "00101110"=>led<="10010010"; --5

when "00110110"=>led<="10000010"; --6

when "00111101"=>led<="11111000"; --7

when "00111110"=>led<="10000000"; --8

when "01000110"=>led<="10010000"; --9

when "00011100"=>led<="10001000"; --A

when "00110010"=>led<="10000011"; --B

when "00100001"=>led<="11000110"; --C

when "00100011"=>led<="10100001"; --D

when "00100100"=>led<="10000110"; --E

when "00101011"=>led<="10001110"; --F

when "00110100"=>led<="11000010"; --G

when "00110011"=>led<="10001001"; --H

when "01000011"=>led<="01111001"; --I

when "00111011"=>led<="11100001"; --J

when "01000010"=>led<="00001001"; --K

when "01001011"=>led<="11000111"; --L

when "00111010"=>led<="10110110"; --M

when "00110001"=>led<="10101011"; --N

when "01000100"=>led<="10100011"; --O

when "01001101"=>led<="10001100"; --P

when "00010101"=>led<="01000000"; --Q

when "00101101"=>led<="10001010"; --R

when "00011011"=>led<="00010010"; --S

when "00101100"=>led<="10000111"; --T

when "00111100"=>led<="11100011"; --U

when "00101010"=>led<="01100011"; --V

when "00011101"=>led<="10010100"; --W

when "00100010"=>led<="11001001"; --X

when "00110101"=>led<="10010001"; --Y

when "00011010"=>led<="00100100"; --Z

when others=>led<="10111111";

end case;

end process;
Симулационното изпалнение на програмата е показано на долната фигура. От нея ясно се виждат етапите на преобразуване и прехвърлянне на данните.

За целта на симулирането е използван допълнителен VHDL test bench source код. Някой от сигналите умишлено са описани като входно/изходни. Това е направено с цел те да могат да се визуализират и по този начин да илюстрират пълното действие на програмата.


Синтезира се модула на клавиатурата и се получава следното :

Release 12.3 - xst M.70d (nt64)

Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.

--> Parameter TMPDIR set to xst/projnav.tmp

Total REAL time to Xst completion: 0.00 secs

Total CPU time to Xst completion: 0.51 secs

--> Parameter xsthdpdir set to xst

Total REAL time to Xst completion: 0.00 secs

Total CPU time to Xst completion: 0.51 secs

--> Reading design: keyboard.prj
TABLE OF CONTENTS

1) Synthesis Options Summary

2) HDL Compilation

3) Design Hierarchy Analysis

4) HDL Analysis

5) HDL Synthesis

5.1) HDL Synthesis Report

6) Advanced HDL Synthesis

6.1) Advanced HDL Synthesis Report

7) Low Level Synthesis

8) Partition Report

9) Final Report

9.1) Device utilization summary

9.2) Partition Resource Summary

9.3) TIMING REPORT

=========================================================================

* Synthesis Options Summary *

=========================================================================

---- Source Parameters

Input File Name : "keyboard.prj"

Input Format : mixed

Ignore Synthesis Constraint File : NO


---- Target Parameters

Output File Name : "keyboard"

Output Format : NGC

Target Device : xc3s500e-5-fg320


---- Source Options

Top Module Name : keyboard

Automatic FSM Extraction : YES

FSM Encoding Algorithm : Auto

Safe Implementation : No

FSM Style : LUT

RAM Extraction : Yes

RAM Style : Auto

ROM Extraction : Yes

Mux Style : Auto

Decoder Extraction : YES

Priority Encoder Extraction : Yes

Shift Register Extraction : YES

Logical Shifter Extraction : YES

XOR Collapsing : YES

ROM Style : Auto

Mux Extraction : Yes

Resource Sharing : YES

Asynchronous To Synchronous : NO

Multiplier Style : Auto

Automatic Register Balancing : No
---- Target Options

Add IO Buffers : YES

Global Maximum Fanout : 500

Add Generic Clock Buffer(BUFG) : 24

Register Duplication : YES

Slice Packing : YES

Optimize Instantiated Primitives : NO

Use Clock Enable : Yes

Use Synchronous Set : Yes

Use Synchronous Reset : Yes

Pack IO Registers into IOBs : Auto

Equivalent register Removal : YES


---- General Options

Optimization Goal : Speed

Optimization Effort : 1

Keep Hierarchy : No

Netlist Hierarchy : As_Optimized

RTL Output : Yes

Global Optimization : AllClockNets

Read Cores : YES

Write Timing Constraints : NO

Cross Clock Analysis : NO

Hierarchy Separator : /

Bus Delimiter : <>

Case Specifier : Maintain

Slice Utilization Ratio : 100

BRAM Utilization Ratio : 100

Verilog 2001 : YES

Auto BRAM Packing : NO

Slice Utilization Ratio Delta : 5


=========================================================================

=========================================================================

* HDL Compilation *

=========================================================================

Compiling vhdl file "D:/Desktop/Dian/TU/tu work/MPIS/signs_on_display/signs_on_display/keyboard.vhd" in Library work.

Entity compiled.

Entity (Architecture ) compiled.
=========================================================================

* Design Hierarchy Analysis *

=========================================================================

Analyzing hierarchy for entity in library (architecture ).

=========================================================================

* HDL Analysis *

=========================================================================

Analyzing Entity in library (Architecture ).

WARNING:Xst:819 - "D:/Desktop/Dian/TU/tu work/MPIS/signs_on_display/signs_on_display/keyboard.vhd" line 19: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:

Entity analyzed. Unit generated.

=========================================================================

* HDL Synthesis *

=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit .

Related source file is "D:/Desktop/Dian/TU/tu work/MPIS/signs_on_display/signs_on_display/keyboard.vhd".

WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Found 4-bit register for signal .

Found 8-bit register for signal .

Found 8-bit register for signal .

Found 4-bit comparator greatequal for signal created at line 28.

Found 1-bit register for signal .

Found 4-bit comparator less for signal created at line 28.

Found 4-bit up counter for signal .

Found 4-bit up counter for signal .

Summary:


inferred 2 Counter(s).

inferred 21 D-type flip-flop(s).

inferred 2 Comparator(s).

Unit synthesized.

=========================================================================

HDL Synthesis Report


Macro Statistics

# Counters : 2

4-bit up counter : 2

# Registers : 11

1-bit register : 9

4-bit register : 1

8-bit register : 1

# Comparators : 2

4-bit comparator greatequal : 1

4-bit comparator less : 1


=========================================================================
=========================================================================

* Advanced HDL Synthesis *

=========================================================================

=========================================================================

Advanced HDL Synthesis Report
Macro Statistics

# Counters : 2

4-bit up counter : 2

# Registers : 21

Flip-Flops : 21

# Comparators : 2

4-bit comparator greatequal : 1

4-bit comparator less : 1


=========================================================================
=========================================================================

* Low Level Synthesis *

=========================================================================
Optimizing unit ...
Mapping all equations...

Building and optimizing final netlist ...

Found area constraint ratio of 100 (+ 5) on block keyboard, actual ratio is 1.
Final Macro Processing ...
=========================================================================

Final Register Report


Macro Statistics

# Registers : 29

Flip-Flops : 29
=========================================================================
=========================================================================

* Partition Report *

=========================================================================
Partition Implementation Status

-------------------------------


No Partitions were found in this design.
-------------------------------
=========================================================================

* Final Report *

=========================================================================

Final Results

RTL Top Level Output File Name : keyboard.ngr

Top Level Output File Name : keyboard

Output Format : NGC

Optimization Goal : Speed

Keep Hierarchy : No
Design Statistics

# IOs : 31


Cell Usage :

# BELS : 84

# GND : 1

# INV : 2

# LUT2 : 8

# LUT3 : 16

# LUT4 : 50

# MUXF5 : 6

# VCC : 1

# FlipFlops/Latches : 29

# FD : 3

# FD_1 : 4

# FDE_1 : 16

# FDR : 1

# FDRE : 4

# FDSE_1 : 1

# Clock Buffers : 1

# BUFGP : 1

# IO Buffers : 29

# IBUF : 1

# OBUF : 28

=========================================================================


Device utilization summary:

---------------------------


Selected Device : 3s500efg320-5
Number of Slices: 43 out of 4656 0%

Number of Slice Flip Flops: 29 out of 9312 0%

Number of 4 input LUTs: 76 out of 9312 0%

Number of IOs: 31

Number of bonded IOBs: 30 out of 232 12%

Number of GCLKs: 1 out of 24 4%


---------------------------

Partition Resource Summary:

---------------------------
No Partitions were found in this design.
---------------------------

=========================================================================

TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT

GENERATED AFTER PLACE-and-ROUTE.
Clock Information:

------------------

-----------------------------------+------------------------+-------+

Clock Signal | Clock buffer(FF name) | Load |

-----------------------------------+------------------------+-------+

ps2clk | BUFGP | 29 |

-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:

----------------------------------------

No asynchronous control signals found in this design
Timing Summary:

---------------

Speed Grade: -5
Minimum period: 3.093ns (Maximum Frequency: 323.269MHz)

Minimum input arrival time before clock: 3.615ns

Maximum output required time after clock: 9.477ns

Maximum combinational path delay: No path found


Timing Detail:

--------------

All values displayed in nanoseconds (ns)
=========================================================================

Timing constraint: Default period analysis for Clock 'ps2clk'

Clock period: 3.093ns (frequency: 323.269MHz)

Total number of paths / destination ports: 86 / 53

-------------------------------------------------------------------------

Delay: 3.093ns (Levels of Logic = 1)

Source: ready (FF)

Destination: temp_0 (FF)

Source Clock: ps2clk falling

Destination Clock: ps2clk falling


Data Path: ready to temp_0

Gate Net


Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

FDSE_1:C->Q 8 0.514 0.673 ready (ready)

LUT3:I2->O 4 0.612 0.499 temp_or00001 (temp_or0000)

FDRE:R 0.795 temp_0

----------------------------------------

Total 3.093ns (1.921ns logic, 1.172ns route)

(62.1% logic, 37.9% route)


=========================================================================

Timing constraint: Default OFFSET IN BEFORE for Clock 'ps2clk'

Total number of paths / destination ports: 6 / 6

-------------------------------------------------------------------------

Offset: 3.615ns (Levels of Logic = 2)

Source: data (PAD)

Destination: temp_0 (FF)

Destination Clock: ps2clk falling


Data Path: data to temp_0

Gate Net


Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

IBUF:I->O 3 1.106 0.603 data_IBUF (data_IBUF)

LUT3:I0->O 4 0.612 0.499 temp_or00001 (temp_or0000)

FDRE:R 0.795 temp_0

----------------------------------------

Total 3.615ns (2.513ns logic, 1.102ns route)

(69.5% logic, 30.5% route)


=========================================================================

Timing constraint: Default OFFSET OUT AFTER for Clock 'ps2clk'

Total number of paths / destination ports: 260 / 28

-------------------------------------------------------------------------

Offset: 9.477ns (Levels of Logic = 6)

Source: code_1 (FF)

Destination: led<3> (PAD)

Source Clock: ps2clk falling


Data Path: code_1 to led<3>

Gate Net


Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

FDE_1:C->Q 28 0.514 1.224 code_1 (code_1)

LUT4:I0->O 1 0.612 0.387 led<5>2_SW0 (N49)

LUT4:I2->O 4 0.612 0.568 led<5>2 (N4)

LUT4:I1->O 2 0.612 0.532 led<3>43 (led<3>43)

LUT3:I0->O 1 0.612 0.000 led<3>178_F (N96)

MUXF5:I0->O 1 0.278 0.357 led<3>178 (led_3_OBUF)

OBUF:I->O 3.169 led_3_OBUF (led<3>)

----------------------------------------

Total 9.477ns (6.409ns logic, 3.068ns route)

(67.6% logic, 32.4% route)


=========================================================================

Total REAL time to Xst completion: 8.00 secs

Total CPU time to Xst completion: 8.77 secs

-->
Total memory usage is 245080 kilobytes


Number of errors : 0 ( 0 filtered)

Number of warnings : 2 ( 0 filtered)

Number of infos : 0 ( 0 filtered)


Преобразуване на кода в код за визуализиране през монитор (Пиксел генератор)
Преобразуването на информацията всъщност се състои основно в преобразуването на входната информация в нива на изходните сигнали за съответния пиксел от монитора. Позицията на самия пиксел се определя от броячите на цолоните и на редовете.

Принципа се състои в обхождане на редовете един по един до пълното запълване на екрана.

Това става като след получаването на данните от клавиатурата, те се разпознават и се зареждат в работни клетки.

----------------------------------------------------------------------------------

-- Company:

-- Engineer:

--

-- Create Date: 02:29:14 04/18/2011



-- Design Name:

-- Module Name: converter - Behavioral

-- Project Name:

-- Target Devices:

-- Tool versions:

-- Description:

--

-- Dependencies:



--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

----------------------------------------------------------------------------------



library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

use ieee.numeric_std.all;

entity converter is

port(clk:in std_logic;

code:in std_logic_vector(7 downto 0);

red, green, blue : out std_logic;

row : in std_logic_vector(8 downto 0);

column : in std_logic_vector(9 downto 0)

);

end converter;


architecture frame of converter is

signal vgad: std_logic_vector(7 downto 0);

signal col : std_logic_vector(9 downto 0):=(others=>'0');

shared variable vard: natural :=0;


begin
process (code, clk, column, row)
begin

if (clk'event and clk='1') then

if (code = "01000110") then

case row is

when "000000000"=>vgad<="00000000"; -- 0

when "000000001"=>vgad<="00000000"; -- 1

when "000000010"=>vgad<="01111100"; -- 2 *****

when "000000011"=>vgad<="11000110"; -- 3 ** **

when "000000100"=>vgad<="11000110"; -- 4 ** **

when "000000101"=>vgad<="11000110"; -- 5 ** **

when "000000110"=>vgad<="01111110"; -- 6 ******

when "000000111"=>vgad<="00000110"; -- 7 **

when "000001000"=>vgad<="00000110"; -- 8 **

when "000001001"=>vgad<="00000110"; -- 9 **

when "000001010"=>vgad<="00001100"; -- a **

when "000001011"=>vgad<="01111000"; -- b ****

when "000001100"=>vgad<="00000000"; -- c

when "000001101"=>vgad<="00000000"; -- d

when "000001110"=>vgad<="00000000"; -- e

when "000001111"=>vgad<="00000000"; -- f

when others=>vgad<="00000000";

end case;

if (column<"0000000000") then

vard:=0;


else

vard:=vard+1;

if (vard=7) then vard:=0;

end if;


end if;

red<=vgad(vard);

green<=vgad(vard);

blue<=vgad(vard);

end if;

end if;


end process;
end frame;

Резултатът след синтеза е:


Release 12.3 - xst M.70d (nt)

Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.

--> Parameter TMPDIR set to xst/projnav.tmp

Total REAL time to Xst completion: 1.00 secs

Total CPU time to Xst completion: 0.83 secs

--> Parameter xsthdpdir set to xst

Total REAL time to Xst completion: 1.00 secs

Total CPU time to Xst completion: 0.84 secs

--> Reading design: converter.prj
TABLE OF CONTENTS

1) Synthesis Options Summary

2) HDL Compilation

3) Design Hierarchy Analysis

4) HDL Analysis

5) HDL Synthesis

5.1) HDL Synthesis Report

6) Advanced HDL Synthesis

6.1) Advanced HDL Synthesis Report

7) Low Level Synthesis

8) Partition Report

9) Final Report

9.1) Device utilization summary

9.2) Partition Resource Summary

9.3) TIMING REPORT

=========================================================================

* Synthesis Options Summary *

=========================================================================

---- Source Parameters

Input File Name : "converter.prj"

Input Format : mixed

Ignore Synthesis Constraint File : NO


---- Target Parameters

Output File Name : "converter"

Output Format : NGC

Target Device : xc3s500e-5-fg320


---- Source Options

Top Module Name : converter

Automatic FSM Extraction : YES

FSM Encoding Algorithm : Auto

Safe Implementation : No

FSM Style : LUT

RAM Extraction : Yes

RAM Style : Auto

ROM Extraction : Yes

Mux Style : Auto

Decoder Extraction : YES

Priority Encoder Extraction : Yes

Shift Register Extraction : YES

Logical Shifter Extraction : YES

XOR Collapsing : YES

ROM Style : Auto

Mux Extraction : Yes

Resource Sharing : YES

Asynchronous To Synchronous : NO

Multiplier Style : Auto

Automatic Register Balancing : No
---- Target Options

Add IO Buffers : YES

Global Maximum Fanout : 500

Add Generic Clock Buffer(BUFG) : 24

Register Duplication : YES

Slice Packing : YES

Optimize Instantiated Primitives : NO

Use Clock Enable : Yes

Use Synchronous Set : Yes

Use Synchronous Reset : Yes

Pack IO Registers into IOBs : Auto

Equivalent register Removal : YES


---- General Options

Optimization Goal : Speed

Optimization Effort : 1

Keep Hierarchy : No

Netlist Hierarchy : As_Optimized

RTL Output : Yes

Global Optimization : AllClockNets

Read Cores : YES

Write Timing Constraints : NO

Cross Clock Analysis : NO

Hierarchy Separator : /

Bus Delimiter : <>

Case Specifier : Maintain

Slice Utilization Ratio : 100

BRAM Utilization Ratio : 100

Verilog 2001 : YES

Auto BRAM Packing : NO

Slice Utilization Ratio Delta : 5


=========================================================================

=========================================================================

* HDL Compilation *

=========================================================================

Compiling vhdl file "C:/Users/mpis/Desktop/MBM-43A/mpis/finale_grande/finale_grande1.vhd" in Library work.

Entity compiled.

Entity (Architecture ) compiled.
=========================================================================

* Design Hierarchy Analysis *

=========================================================================

Analyzing hierarchy for entity in library (architecture ).

=========================================================================

* HDL Analysis *

=========================================================================

Analyzing Entity in library (Architecture ).

WARNING:Xst:790 - "C:/Users/mpis/Desktop/MBM-43A/mpis/finale_grande/finale_grande1.vhd" line 60: Index value(s) does not match array range, simulation mismatch.

WARNING:Xst:790 - "C:/Users/mpis/Desktop/MBM-43A/mpis/finale_grande/finale_grande1.vhd" line 61: Index value(s) does not match array range, simulation mismatch.

WARNING:Xst:790 - "C:/Users/mpis/Desktop/MBM-43A/mpis/finale_grande/finale_grande1.vhd" line 62: Index value(s) does not match array range, simulation mismatch.

Entity analyzed. Unit generated.

=========================================================================

* HDL Synthesis *

=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit .

Related source file is "C:/Users/mpis/Desktop/MBM-43A/mpis/finale_grande/finale_grande1.vhd".

WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:1780 - Signal

  1   2



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